In the fabrication of integrated circuits (ICs), trench isolation is frequently used to replace more conventional local oxidation of silicon in order to form improved field isolation structures. In the formation of such trench isolation structures shown in FIG. 1A, a pad oxide 110 is first grown over a silicon substrate 115, which is followed by the deposition of a silicon nitride layer 120. The silicon nitride layer 120 is patterned, typically with a photoresist 123, to form a trench 125, after which, the photoresist 123 is removed and an oxide liner 130 is then subsequently formed in the trench 125. This is followed by a wet etch nitride pullback process, which pulls the nitride back from the edge of the trench 125 and well within an active area 127, as shown in FIG. 1B. The nitride pullback is achieved with a combination of hydrofluoric acid (HF) and phosphoric acid used in sequence. During the nitride pullback, it is important to note that a portion of the oxide liner 130 can be removed, which will cause the oxide liner 130 to recede within the trench, as illustrated. As discussed below, this removal or thinning of the oxide liner 130 is undesirable.
Next, as illustrated in FIG. 1C, a high-density plasma deposition process is conducted to fill the trench 125 with an oxide 135. Following this deposition step, the excess oxide 135 is removed via a chemical mechanical polishing (CMP) process, and the silicon nitride layer 120 is removed. Following the nitride pullback, the pad oxide 110 layer is removed, which results in a trench isolation structure 140 shown in FIG. 1C. A gate oxide process is then conducted to obtain a high quality gate oxide for the later deposited gate.
Several problems arise, however, with this process that the industry is presently seeking to improve. For example, during the oxide liner anneal step, a portion of the silicon nitride layer is converted to an oxy-nitride that creates a variably thick oxy-nitride layer. This oxy-nitride layer can cause significant variation in the subsequent wet etch rate of the silicon nitride layer. This, in turn, can become a problem for subsequent processes because a targeted amount of the silicon nitride layer may or may not be achieved.
Typically, it is desirable to leave a targeted amount of silicon nitride on the substrate for CMP purposes because it serves as a stopping layer for the oxide removal. If the amount of nitride present varies due to the variation in the wet etch rate, errors may be introduced in the amount of oxide removed during the CMP process, resulting in varying levels of planarization. This, in turn, will result in undesirable variations in the isolation of the transistors across a wafer or a device.
In addition, the HF treatment leads to a loss or thinning of the liner oxide near the silicon edges of the trench. This can be a problem because the loss or thinning of the liner oxide at the edges can ultimately cause leakage in the device. Further, the removal of the pad oxide 110 and the process used to form the gate oxide creates divots 145 on the sides of the trench isolation structure 140 due to the loss of oxide during these steps, as shown in FIG. 1D. These divots 145 can extend below the upper edge of an active area 150. When the polysilicon is deposited over this structure, the amount of polysilicon in the divots 145 may be twice as much as the polysilicon over the active region 150 where the gate is to be formed. This significant difference in the thickness of the polysilicon makes subsequent etching of the gates more difficult because the polysilicon in the divots 145, which is thicker than the polysilicon over the active area 150, must be removed. This, in turn, makes gate definition more difficult because the critical dimensions of the gate may vary and may not be well controlled due to the removal of the excess polysilicon around the divot areas. Loss of control of the gate dimensions at the edge of the active region can lead to excessive transistor leakage current as well as other yield loss due to mismatched transistor performance.
Therefore what is needed in the art is a method that avoids the disadvantages associated with these prior art processes.